A 22 Gbit/s PAM-4 receiver in 90 nm CMOS-SOI technology

Author

Toifl, Thomas ; Menolfi, Christian ; Ruegg, Michael ; Reutemann, Robert ; Buchmann, Peter ; Kossel, Marcel ; Morf, Thomas ; Schmatz, Martin

Author_Institution

IBM Zurich Res. Lab., Ruschlikon, Switzerland

fYear

2005

fDate

16-18 June 2005

Firstpage

380

Lastpage

383

Abstract

A receiver for PAM-4 encoded data signals is presented, which was measured to receive data at 22 Gbit/s with a BER <10^-12 at a maximum frequency deviation of 350 ppm and a 2⁷-1 PRBS pattern. We propose a novel voltage shifting amplifier to introduce a programmable offset to the differential data signal. A CML biasing scheme using programmable matched resistors limits the effect of process variations. The receiver also features a programmable signal termination, an analog equalizer and offset compensation for each sampling latch. Measured current consumption is 207 mA from a 1.1 V supply, active chip area is 0.12 mm².

Keywords

CMOS integrated circuits; current-mode logic; digital communication; integrated circuit design; pulse amplitude modulation; receivers; silicon-on-insulator; 1.1 V; 207 mA; 22 Gbit/s; 90 nm; CML biasing scheme; CMOS-SOI technology; PAM-4 encoded data signals; PAM-4 receiver; analog equalizer; current mode logic; differential data signal; digital communication; offset compensation; programmable matched resistors; programmable offset; programmable signal termination; sampling latch; serial links; voltage shifting amplifier; Area measurement; Bit error rate; CMOS technology; Current measurement; Differential amplifiers; Equalizers; Frequency measurement; Resistors; Signal sampling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on

Print_ISBN

4-900784-01-X

Type

conf

DOI

10.1109/VLSIC.2005.1469409

Filename

1469409