The design verification for the 3DES encipher chip based on an extended Petri net and XML/Java executor

Author

Yamaguchi, Shin Nosuke ; Nishino, Akira ; Wasaki, Katsumi ; Shidama, Yasunari

Author_Institution

Kyusyu Inst. of Technol., Fukuoka, Japan

Volume

3

fYear

2004

fDate

6-9 Dec. 2004

Firstpage

1994

Abstract

In this paper, we propose the new method for the parallel system design based on expanded the logical coloured Petri net (LCPN). An LCPN is an extended Petri net that solves the problem of system description in previously proposed place/transition nets and coloured Petri nets. This extension of Petri nets is suitable for designing complex control systems and for discussing methods of evaluating such systems realistically. In order to study the behaviour of the server system modelled with this net we simulated a Java program. This program confirmed that this extended Petri net is an effective tool for modelling the parallel system.

Keywords

Java; Petri nets; XML; control system CAD; digital simulation; graph colouring; parallel programming; program verification; 3DES encipher chip; Java executor; Java program simulation; XML; complex control systems; design verification; extended Petri net; logical coloured Petri net; parallel system design; parallel system modelling; place/transition nets; server system behaviour; system description; Control systems; Costs; Design engineering; Java; Parallel programming; Petri nets; Software design; System recovery; System software; XML;

fLanguage

English

Publisher

ieee

Conference_Titel

Control, Automation, Robotics and Vision Conference, 2004. ICARCV 2004 8th

Print_ISBN

0-7803-8653-1

Type

conf

DOI

10.1109/ICARCV.2004.1469468

Filename

1469468