A high speed 3.3V IO buffer with 1.9V tolerant CMOS process

This paper presents a 3.3V IO buffer design using 1.9V MOS transistors in 0.21µm process with 40A^ogate oxide thickness. The circuit is implemented using cascoded MOS transistors between bond pad and power supply terminals. Gates of cascoded transistors are biased dynamically to alleviate the problem of reduction in reliability of MOS elements due to gate oxide stress during signal overshoots at the bond pad. Various design techniques are used in pre-driver circuits for voltage translation, low power, signal integrity and reliability of MOS components. The design has been successfully implemented in a 400MHz UltraSPARC microprocessor.