A single-ended 1.5 GHz 8/9 dual-modulus prescaler in 0.7 µm CMOS with low phase noise and high input sensitivity

A dual-modulus divide-by-8/9 prescaler fabricated in a standard 0.7µm CMOS technology is presented. A high speed, single-ended divide-by-2 D-flipflop is realized, based on TSPC (True Single Phase Clock) logic. The circuit minimizes phase noise and exhibits an excellent input sensitivity, without using input buffering nor single-ended to differential conversion. The measured maximum input frequency of the prescaler is 1.5 GHz at a 5V power supply, while consuming 11mA. The minimum required input level is smaller than 110mVrmsover the whole operating range. Measured phase noise is as low as -112 dBc/Hz at 1 kHz and -163 dBc/Hz at large offset frequencies.