Title :
25th ACM/IEEE Design Automation Conference. Proceedings 1988 (Cat. No.88CH2540-3)
Abstract :
The following topics are dealt with: design for testability: VHDL in use; floorplanning and area estimation; automatic test generation; hardware design languages and environments; physical design acceleration; parallel simulation; channel and global routing; mega-simulation accelerators; Xerox PARC design automation system; engineering information databases; application-specific simulation; placement algorithms; high level synthesis; distributed databases for the support of design teams; DA for analog circuits; layout compaction; register-transfer-level synthesis; logic synthesis and optimization; transistor-level-layout; physical design verification; incremental techniques in logic simulation; and gate extraction and connectivity verification. Abstracts of individual papers can be found under the relevant classification codes in this or other issues
Keywords :
VLSI; circuit layout CAD; integrated logic circuits; VHDL; Xerox PARC design automation system; analog circuits; application-specific simulation; area estimation; automatic test generation; channel routing; circuit layout CAD; conference 1988; design for testability; distributed databases; engineering information databases; floorplanning; gate connectivity verification; gate extraction; global routing; hardware design languages; high level synthesis; incremental techniques; layout compaction; logic simulation; logic synthesis; mega-simulation accelerators; parallel simulation; physical design acceleration; physical design verification; placement algorithms; register-transfer-level synthesis; transistor-level-layout;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14725
