Title :
An automated BIST approach for general sequential logic synthesis
Author_Institution :
AT&T Bell Lab., Naperville, IL, USA
Abstract :
An automated built-in self-test (BIST) technique for general sequential logic is described. This approach has been incorporated in a behavioral model synthesis system, providing automated implementation of BIST in very-large-scale-integration (VLSI) devices as well as programmable-logic-device (PLD)-based circuit packs. BIST can be directly used at all levels of testing from device testing through system diagnostics. It is based on selective replacement of existing system memory elements with BIST flip-flop cells that are connected to form a circular chain, performing data compaction and test pattern generation simultaneously. Two production VLSI devices have been implemented with this automated BIST approach. In each case, the total fault coverage was in excess of 96% and the logic overhead incurred was between 9.7 and 18.9%
Keywords :
VLSI; integrated circuit technology; integrated circuit testing; integrated logic circuits; BIST flip-flop cells; PLD; all levels of testing; automated BIST approach; automated implementation of BIST; behavioral model synthesis system; built-in self-test; circular chain; data compaction; design for testability; device testing; general sequential logic synthesis; logic overhead; production VLSI devices; programmable-logic-device; selective replacement of existing system memory elements; system diagnostics; test pattern generation; total fault coverage; very-large-scale-integration; Built-in self-test; Circuit synthesis; Circuit testing; Compaction; Flip-flops; Logic devices; Performance evaluation; System testing; Test pattern generators; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14726
