Title :
A defect-tolerant and fully testable PLA
Author :
Wehn, N. ; Glesner, M. ; Caesar, K. ; Mann, P. ; Roth, A.
Author_Institution :
Inst. fuer Halbleitertech., Tech. Hochschule Darmstadt, West Germany
Abstract :
The authors present a defect-tolerant and fully testable programmable logic array (PLA) that allows the repair of a defective chip. The repair process is described. Special emphasis is placed on the location of defects inside a PLA. The defect location mechanism is completely topological and circuit-independent and therefore easy to adapt to existing PLA generators. Yield considerations for this type of PLA are presented.<>
Keywords :
VLSI; cellular arrays; fault location; integrated logic circuits; VLSI; defect location mechanism; defect tolerant PLA; design for testability; fully testable PLA; location of defects; programmable logic array; repair process; yield; Automatic testing; Circuit faults; Circuit testing; Decoding; Delay effects; Fault location; Hardware; Logic circuits; Programmable logic arrays; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14729
