Monolithic integration of InGaAs/InP PIN photodiode with self-aligned junction FETs

The fabrication of a monolithically integrated receiver optoelectronic integrated circuit(OEIC) using an InGaAs/InP PIN photodiode (PD), self-aligned junction FETs, and a bias resistor oil a semi-insulating InP substrate is described. The fabrication process is shown to be highly compatible between the PD and the self-aligned JFET, and reduction in gate length is achieved using anisotropic selective etching, and a nonplanar organometallic vapor-phase epitaxy (OMVPE) process. The PIN detector with a 80-μm diameter exhibits a leakage current of 2 nA and a capacitance of about 0.35 pF at -5 V bias voltage. The extrinsic transconductance and gate-source capacitance of the JFET are typically 45 mS/mm and 4.0 pF/mm at 0 V respectively. The maximum voltage gain of the preamplifier is 12.5, and the bandwidth of the PIN-amplifier OEIC is expected to be about 1.2 GHz