Title :
VHDL: a call for standards
Author :
Coelho, David R.
Author_Institution :
Vantage Anal. Syst., Inc., Fremont, CA, USA
Abstract :
VHDL (VHSIC Hardware Description Language) is such an extremely flexible and versatile language, that the language reference documentation is not sufficient to ensure that models written by one hardware designer will be compatible with another´s models. What is required is a set of VHDL modeling conventions and standard packages which structure the usage of VHDL modeling approaches. The issues inherent in VHDL in regards to model compatibility are discussed, and a number of solutions to this problem
Keywords :
VLSI; logic CAD; specification languages; standards; VHDL; VHSIC Hardware Description Language; flexible language; language reference documentation; model compatibility; set of VHDL modeling conventions; solutions; standard packages; standards; versatile language; Computer languages; Delay effects; Documentation; Hardware; Logic design; Logic devices; Programming profession; Propagation delay; Software engineering; Timing;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14732
