Silicon planar integrated circuitry - Using a unique combination of multi-layer epitaxial and diffusion techniques

A combination of multi-layer epitaxial growth and selective diffusion was successfully used to fabricate electrically isolated active devices on a single chip of silicon. Four, layer silicon epitaxial growth is used in our present devices. Electrical isolation of multi-layer structures can be obtained by making impurity depositions at the junctions, or within epitaxial layers. For example, two epitaxial layers can be isolated in the following way. A p-type deposition is placed on a p-type substrate. Two epitaxial layers are then grown first, n-type, and then p-type, after which, an n-type deposition is placed on the surface. This technique is, of course, not limited to isolating epitaxial layers. The ability to work within the solid offers new design freedom. For example, reverse impurity profiles can be readily obtained.