Title :
A module area estimator for VLSI layout
Author :
Chen, Xinghao ; Bushnell, Mchael L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
Abstract :
An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors´ layout area estimates are very close to those of manually laid out modules.<>
Keywords :
VLSI; circuit layout CAD; VLSI chip layout; VLSI layout; area estimation; chip floor plan; design iterations reduction; full-custom layout; layout area estimates; module area estimator; standard cell layout; CMOS technology; Chip scale packaging; Design automation; Logic functions; Process planning; Routing; Shape; Very large scale integration; Wire; Wiring;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14734
