Title :
A new area and shape function estimation technique for VLSI layouts
Author :
Zimmerman, Gerhard
Author_Institution :
FB Inf., Kaiserslautern Univ., West Germany
Abstract :
Area estimation of IC layouts has become an important requirement for early design and top-down chip planning tools. Especially the relation of area and aspect ratio (shape function) is necessary for chip planning. Statistical models have been published with good results for standard cell blocks with near unity aspect ratios. A model is presented for the prediction of shape functions for aspect ratios up to 1:5. The model is based on the shape and connectivity of adjacent cells. It can be used for many different design styles and has been tested for standard cell blocks for the placement of general cells
Keywords :
VLSI; circuit layout CAD; IC layouts; VLSI layouts; aspect ratio; connectivity of adjacent cells; design styles; placement of general cells; shape function estimation technique; standard cell blocks; top-down chip planning tools; Circuit testing; Geometry; Logic design; Predictive models; Routing; Shape; Solid modeling; Standards publication; Very large scale integration; Wiring;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14735
