A new technique for preparing oxide-isolated silicon wafers for microcircuits

A technique has been developed for preparing oxide-isolated silicon structures for use in fabrication of monolithic silicon microcircuits. In contrast to the techniques initially described for obtaining oxide-isolated structures, completely flat wafers containing patterns of oxide-isolated silicon regions can be produced without resorting to lapping or polishing operations. Resulting microcircuits, similar to those prepared by more critical and more cosily oxide-isolation techniques, possess all of the advantages over circuits in which isolation is obtained by reverse biasing of pn junctions, including low parasitic capacitance, high dielectric breakdown, and low leakage current. The new technique is compared with previously-described sequences for obtaining oxide-isolated silicon structures by the steps of selective etching of an isolation pattern followed by thermal oxidation, vapor plating of polycrystalline silicon, and precision lapping and polishing. It is shown that the thickness of the n-type layer in, for example, circuits in which the transistors are prepared by double diffusion into n-type isolated regions with underlying n⁺layers, can be controlled within a few microns over a wafer 3 cm in diameter. Accurate control of the n layer thickness does not require control of thickness and parallelism during lapping and mechanical polishing, or precise control of chemical etching of silicon. The feasibility of the new approach has been demonstrated with a number of structure.