Abstract :
A distributed model of a transistor which takes into account the lateral voltage drop across the emitter width is described. The distributed equivalent is obtained by dividing the active transistor into small sections, each of which is then represented by a π-equivalent lumped transistor. Other phenomena incorporated in this model are: 1. Base stretching into the collector region at high current densities 2. Conductivity modulation in the base region 3. Storage of mobile carriers in the depletion regions 4. Base width modulation because of collector base bias 5. Voltage dependence of junction capacitances 6. Injection dependence of semiconductor parameters 7. Surface effects A computer program which solves for transient, dc, and ac response for the above transistor model in common-emitter configuration is also presented. The inputs for this program (besides external circuit parameters) are: 1. Transistor horizontal geometry 2. Transistor impurity profile 3. Semiconductor parameters This program was used to design and fabricate a silicon transistor with Ft1.8 gHzat VCB= 0. Effect of variations in horizontal geometry and impurity profile on switching speeds are quantitatively shown and are compared with present state-of-the-art transistors. Additionally, this Program will enable us to custom-design transistors, to pin-point the most promising area of transistor research, and, finally, to indicate the ultimate limit (speed) of silicon transistors.
