Silicon controlled rectifiers in monolithic integrated circuits

Silicon controlled rectifiers employing a planar NPN transistor structure and a lateral PNP structure have been fabricated by epitaxial and diffusion techniques into a single four layer structure in an isolation region. Fabrication steps are completely compatible with the fabrication of other standard integrated circuit components. Effective isolation between SCR devices is obtained using standard junction-type isolation. A high concentration deep N+ subdiffusion is employed under the lateral SCR device to minimize the current gain of the parasitic PNP transistor consisting of the P-type anode of the SCR, the N-type epitaxial layer and the P-type substrate. Degradation of both the SCR blocking voltage capabilities and dV/dt (anode to cathode voltage rise rate) rating and excessive power dissipation result at the isolation junction if the parasitic current gain from the anode to substrate is high. Typical SCR characteristics include greater than 50 volts breakover voltage, under 1.8 volts forward voltage at 300 milliamperes load current, under .2 millamperes gate current with a greater than 10V/usec dV/dt at 150°C case temperature.