Mesa isolation - An isolation technique for integrated circuits

The electrical components of an integrated circuit are presently isolated, using one of the various forms of P-N junction or dielectric isolation. In these techniques, the isolation step is performed prior to the fabrication of the active and passive components such as transistors, diodes, resistors, etc. The objective of this paper is to discuss an isolation technique in which the isolation process steps are performed after the components have been fabricated. These are two major advantages derived from isolating the components after fabrication. First, an ideal wafer surface is available for small geometry photoresist masking. Second, the mesa isolation process requires no process temperature above the silicon-aluminum eutectic temperature and thus the isolation process does not alter diffusion profiles or epitaxial films used for thickness control of transistor collector layers. Another property of the structure is that the device surfaces are buried and this may be useful in low cost packaging. Therefore after the active and passive components have been fabricated (i.e. diffused, deposited, etc.) and interconnected they are ready to begin mesa isolation processing. The wafer is first coated with a dielectric material such as glass and then it is bonded to a substrate. At this point the metal interconnection and device surfaces are buried between the substrate and the wafer. The backside of the wafer is then thinned to the desired thickness, an isolation mask is applied, and the silicon which connects the electrical components is removed by mesa etching. The feasibility of this structure has been demonstrated using a silicon planar -DTµL gate with NiCr thin film resistors.