DocumentCode
3552597
Title
Parallel channel routing
Author
Zargham, Mehdi R.
Author_Institution
Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
fYear
1988
fDate
12-15 Jun 1988
Firstpage
128
Lastpage
133
Abstract
A parallel algorithm is proposed for the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. The approach does not impose restrictions on the channel type (such as fixed or variable channel widths) and the number of available layers. The algorithm contains three major phases: (1) dividing the channel into several regions by selecting some columns, (2) assigning tracks to nets of the selected columns, and (3) assigning tracks to nets of the columns in each region
Keywords
VLSI; circuit layout CAD; parallel processing; circuit layout CAD; design of VLSI chips; parallel algorithm; parallel channel routing; shared-memory multiprocessor environment; switchbox routing; Algorithm design and analysis; Computer science; Parallel algorithms; Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14747
Filename
14747
Link To Document