Title :
On path selection in combinational logic circuits
Author :
Li, Wing Ning ; Reddy, Sudhakar M. ; Sahni, Sartaj
Author_Institution :
Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Abstract :
The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate circuit model for such gates. The algorithms are also directly applicable to sequential circuits that use the so-called scan design, since in such circuits it is only necessary to test the combinational circuit embedded between latches.<>
Keywords :
VLSI; logic CAD; logic testing; design automation; minimum cardinality path set; path selection in combinational logic circuits; polynomial-time algorithm; scan design; sequential circuits; timing verification; Circuit testing; Cities and towns; Clocks; Combinational circuits; Computer science; Costs; Instruments; Logic circuits; Propagation delay; Terminology;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14749
