DocumentCode
3552791
Title
An empirical study of on-chip parallelism
Author
Bailey, Mary L. ; Snyder, Lawrence
Author_Institution
Dept. of Comput. Sci., Washington Univ., Seattle, WA, USA
fYear
1988
fDate
12-15 Jun 1988
Firstpage
160
Lastpage
165
Abstract
A methodology is presented for empirically determining the amount of parallelism on a CMOS VLSI chip. Six chips are measured, and the effect of input choice and circuit size is studied. The unexpectedly low parallelism measured here suggests that certain strategies for parallel simulators may be doomed, and earlier efforts to extrapolate parallelism from small circuits to large circuits may have been overly optimistic
Keywords
CMOS integrated circuits; VLSI; decoding; digital filters; digital simulation; microprocessor chips; multiplying circuits; shift registers; CMOS VLSI chip; IIR digital filter; RISC microprocessors; circuit size; decoder; empirical study; multiplier; on-chip parallelism; parallel simulators; shift register; Circuit simulation; Computer science; Distortion measurement; Driver circuits; Parallel processing; Power measurement; Probes; Semiconductor device measurement; Switching circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14752
Filename
14752
Link To Document