An optimal packet switch architecture for ATM

The architecture of a high speed packet switch for an ATM system is presented. The switch is based on input electronic modules, where the incoming packets are processed and buffered, and on an optical interconnection network, connecting the inputs to the outputs. During each slot each output can receive a single packet, and each input can transmit up to L packets. A reservation mechanism avoids collisions on the optical network, implementing a series of distributed queues. The switch performance was studied by simulation. The effect of the input switching capacity L on the performance is discussed