DocumentCode :
3552827
Title :
Bipolar integrated circuits formed in P-type epitaxial layers
Author :
Murphy, B.T.
Volume :
14
fYear :
1968
fDate :
1968
Firstpage :
20
Lastpage :
22
Abstract :
A new integrated circuit fabrication scheme, using transistors with p-type epitaxially grown base layers was proposed by the authors at the 1968 ISSCC. Transistor-transistor logic gates having a packing density of 
gates/in2have been fabricated using this scheme. The gates have a power × delay of 8 picojoules and a delay of 20 nsec using a 1.5 volt power supply. The output transistors have a peak ft of 2-3.4 GHz.
gates/in2have been fabricated using this scheme. The gates have a power × delay of 8 picojoules and a delay of 20 nsec using a 1.5 volt power supply. The output transistors have a peak fKeywords :
Bipolar integrated circuits; Conductivity; Electrodes; Epitaxial layers; FETs; Insulation; Integrated circuit technology; MOSFETs; Silicon; Substrates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1968 International
Type :
conf
DOI :
10.1109/IEDM.1968.187945
Filename :
1475470
Link To Document :
