Title :
The laminated overlay transistor, a status report
Author :
Amantea, R. ; Becke, H.W. ; White, J.P.
Abstract :
Since the Laminated Overlay Transistor (LOT) was first reported at the IEDM in 1967 considerable advances have been made with regard to technology, device design, and performance of this "three-dimensional" transistor structure.
Keywords :
Breakdown voltage; Current measurement; Frequency; Gain measurement; Impurities; Laboratories; Predictive models; Semiconductor process modeling; Substrates; Transistors;
Conference_Titel :
Electron Devices Meeting, 1968 International
DOI :
10.1109/IEDM.1968.187998
