Title :
Multi-pads, single layer power net routing in VLSI circuits
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
An algorithm is presented for obtaining a planar routing of two power nets in building-block layout. In contrast to other works, more than one pad for each of the power nets is allowed. First, conditions are established to guarantee a planar routing. The algorithm consists of three parts, a top-down terminal clustering, a bottom-up topological path routing, and a wire-width calculation procedure. Because of the hierarchical nature of the algorithm, it is inherently fast
Keywords :
VLSI; circuit analysis computing; circuit layout CAD; integrated circuit technology; VLSI circuits; algorithm; bottom-up topological path routing; building-block layout; multipads routing; planar routing; power nets; single layer power net routing; top-down terminal clustering; wire-width calculation procedure; Circuits; Design automation; Routing; Very large scale integration; Wire;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14756
