A high speed protocol processor to execute OSI

Author

Terada, Matsuaki ; Yokoyama, Tatsuya ; Hirata, Tetsuhiko ; Matsui, Susumu

Author_Institution

Hitachi Ltd., Kanagawa, Japan

fYear

1991

fDate

7-11 Apr 1991

Firstpage

944

Abstract

A high-speed open systems interconnection (OSI) protocol processor is described which is intended for use in LAN adapters. The processor uses recently developed hardware for normal data transfer on layer 2 (LLC class 1), layer 3 (CLNP) and layer 4 (TP4). Connection control and abnormal data transfer (i.e. error handling) of OSI are executed by a general purpose microprocessor. In an experimental system, this processor increased OSI processing speed seven to 12 times over conventional systems. The new processor can therefore significantly improve LAN adapter performance by reducing the overhead associated with OSI processing time

Keywords

local area networks; open systems; protocols; telecommunications computing; LAN adapters; OSI; abnormal data transfer; general purpose microprocessor; high speed protocol processor; normal data transfer; open systems interconnection; Error correction; Hardware; LAN interconnection; Local area networks; Microprocessors; Open systems; Protocols; Throughput; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

INFOCOM '91. Proceedings. Tenth Annual Joint Conference of the IEEE Computer and Communications Societies. Networking in the 90s., IEEE

Conference_Location

Bal Harbour, FL

Print_ISBN

0-87942-694-2

Type

conf

DOI

10.1109/INFCOM.1991.147607

Filename

147607