• DocumentCode
    3553114
  • Title

    Design considerations of hyper-abrupt tuning diodes

  • Author

    Kannam, P.J.

  • Volume
    15
  • fYear
    1969
  • fDate
    1969
  • Firstpage
    140
  • Lastpage
    140
  • Abstract
    The voltage variable capacitor promises to be an ideal device for electronic tuning applications. For the best design, the capacitance ratio and the quality factor of the devices should be kept as high as possible over the required voltage range. Furthermore, applications requiring more than one diode generally necessitate that the diodes track each other over the useful operating voltage range. When a high capacitance ratio is desired, it is usually achieved by the formation of a hyper-abrupt junction with a retrograded doping profile on one side. The slope and the doping of the retrograded region as well as the thickness of the high resistivity epitaxial region are the critical parameters determining the device characteristics. A knowledge of the interdependence of these parameters is of fundamental importance for the optimization of the design. This paper describes the computer calculation done for the design of tuning diodes. A hyper-abrupt junction with a retrograded Gaussian profile is considered. The computation consists in establishing the doping profile across the wafer with given values of surface concentration, junction depth and epitaxial background doping. The applied voltage as a function of depletion width is determined and the corresponding junction capacitance evaluated. The quality factor as given by the series resistance is then calculated, taking into account the nonlinear variation of mobility with impurity distribution. The breakdown voltage is computed from the field intensity distribution across the junction and the corresponding impact ionization rate. Calculations are carried out over a wide range of device parameters. The various factors that should be considered for an ideal design are discussed.
  • Keywords
    Capacitance; Capacitors; Conductivity; Design optimization; Diodes; Doping profiles; Impurities; Q factor; Surface resistance; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1969 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1969.188190
  • Filename
    1476071