Abstract :
A 256-bit static COS/MOS (complementary symmetry MOS) random-access memory chip has been fabricated with a 30 mil2cell and a chip size (0.110 × 0.128 inch) basically comparable to that of single-channel static MOS memories. Complementary MOS layouts with both p-channel and n-channel MOS transistors have generally required more area than single-channel MOS devices. A favorable memory cell circuit symmetry and modified layout rules can, however, permit the advantages of a complementary technology without areal penalty.