DocumentCode
3553159
Title
A 1024 bit N-channel MOS read-write memory chip
Author
Krolikowski, W. ; Brown, W. ; Dries, R. ; Foote, R. ; Lund, D. ; Plimley, R. ; Reuter, J. ; Sandhu, J. ; Scow, K. ; Tuttle, J.
Author_Institution
Cogar Corp., Wappingers Falls, N. Y.
Volume
16
fYear
1970
fDate
1970
Firstpage
16
Lastpage
16
Abstract
The Cogar 1024-bit MOS read-write memory chip is fully decoded, has a 100-ns access time, and is only 125 × 125 mils in size. This small size is made possible by the use of a 4-device memory cell and dimensional tolerances as small as 0.15 mil. The chips are fabricated from a 2.25-inch-diameter wafer that consists of a low-resistivity p-type substrate covered by a high-resistivity p-type epitaxial layer. This epitaxial layer provides not only for precise control of surface impurity concentration, but also provides means for a reach-through type of gate protection device. In addition, the low-resistivity substrate tends to minimize unwanted noise voltages due to pulse currents flowing through the substrate.
Keywords
Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1970 International
Type
conf
DOI
10.1109/IEDM.1970.188213
Filename
1476325
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