Author :
Tameda, M. ; Sasaki, Innan ; Shiba, H.
Abstract :
Beam-lead MOS devices have been fabricated using the planar interconnection method, which consists of Al interconnection paths buried in an alumina layer. The technique offers improvement in the threshold stability, packing density, and thermomechanical stress, and freedom from external ionic contamination. The technique is uniquely suited to MOS dynamic memories because of improved integrity of the interconnection paths, lower leakage currents, and improved stability of electrical parameters. This paper illustrates the advantages of the technique through a detailed comparison with conventional MOS methods for constructing a dynamic memory.