The channel-conductance increase of conventional MOS transistors by avalanche injection: Application to read-only memory

The walk-out phenomena of the avalanche breakdown voltage at the drain junction of MOS transistors is caused by injection of hot carriers from the avalanche plasma into the gate oxide. This paper reports detailed data of this phenomenon observed in conventional Al or Si gate, p- and n-channel transistors of a narrow channel, m, aiming at a low-cost, electrically programmable ROM. The p-channel transistor, for example, of 5Ω-cm, n-Si, tox= 3000Å, L = 2µm, W = 50µm, Vth = -4V, can be changed to a completely normally "on" transistor (Vth = 6V), after applying a -96V through a 10kΩ resistor, for 1.5 sec, to the source and drain junctions, the gate electrode being connected to the substrate. The estimated electron density trapped near the Si-SiO2interface is /cm², and the capture probability defined as the ratio of the trapped charges to the integrated avalanche current is . When the gate is biased to +50V in order to accelerate the carrier injection, the necessary pulse duration is down to 120 msec. This can be further lowered by design optimization. For the n-channel transistors the hole injection is about three orders of magnitude lower than the electron injection in the p-channel case, because of higher barrier height for holes (3.8eV) than forelectrons (3.15 eV).