A VLSI architecture for adaptive signal processing

A VLSI architecture for direct parallel implementation of N -tap LMS (least mean square) adaptive filters is presented which uses N multiplier-accumulators and N-1 parallel adders. It will take two multiply delays and log₂ N add delays for each sampled datum. A prototype VLSI processor which can implement 16-tap adaptive filters on a single chip was also developed. The processor has very good architectural features, such as modularity, regularity, and cascadability. By cascading the processors, a very-high-order adaptive filter can be implemented in real time with a several-megahertz sampling rate