Epitaxial V-groove integrated circuit process

A new four-mask epitaxial V-groove (EVG) process for the fabrication of bipolar integrated circuits has been developed. The process utilizes non-critical epitaxial ν/N⁺/N^-layers and anisotropic etching of silicon to eliminate the buried layer and isolation diffusions as well as the need for masking the base diffusion of the standard planar epitaxial bipolar integrated circuit process. NPN transistor, resistor, and Schottky diode characteristics are equivalent to or exceed those of the standard process. Parasitic collector-substrate capacitance is reduced to a minimum by the use of a near-intrinsic (ν) epitaxial layer between the buried layer and substrate. Side-wall capacitance is eliminated completely. Shallower high-voltage structures can be made. Collector series resistance can be reduced significantly by direct contact to the buried layer. The area of an NPN EVG transistor is less than 50% the area of a comparable NPN epitaxial planar device. A five-mask epitaxial V-groove process produces lateral PNP transistors which are superior to those of the four-mask process.