Title :
Probability of latching single event upset errors in VLSI circuits
Author :
Holland, Kenneth Chris ; Tront, Joseph G.
Author_Institution :
Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
Methods are presented that can be used to determine the probability that a SEU (single-event upset) occurring at any node in a circuit will cause an error at the output of a flip-flop. The case when an SEU occurs in a combinational logic circuit is considered. The methods are incorporated into a program, named SUPER II, that is able to evaluate a circuit to determine the nodes with the highest probability of having a SEU cause an error at the output of a flip-flop. After analysis with this program, a designer might make design changes to the circuit to make it less vulnerable to errors. Ten testbench circuits were developed to test SUPER II and to explore the behavior of the transient pulse as it propagates through the combinational logic
Keywords :
VLSI; circuit analysis computing; combinatorial circuits; errors; flip-flops; integrated logic circuits; logic design; probability; transient response; SEU; SUPER II; VLSI circuits; combinational logic circuit; flip-flop output; latching probability; single event upset errors; transient pulse; Capacitance; Circuit faults; Combinational circuits; Computer errors; Flip-flops; Logic; Pulse circuits; Single event upset; Space vector pulse width modulation; Very large scale integration;
Conference_Titel :
Southeastcon '91., IEEE Proceedings of
Conference_Location :
Williamsburg, VA
Print_ISBN :
0-7803-0033-5
DOI :
10.1109/SECON.1991.147715
