Title :
Layout design of VLSI multichip packaging
Author_Institution :
Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA
Abstract :
The nature of multichip module layout is explored, and several associated fundamental design problems are discussed. In particular, problems of decomposing a three-dimensional layout into a set of single-layer layouts and techniques of incorporating performance requirements into a single-layer layout are studied
Keywords :
VLSI; circuit layout; hybrid integrated circuits; integrated circuit technology; modules; packaging; thin film circuits; 3D layout decomposition; MCM technology; VLSI multichip packaging; multichip module layout; performance requirements; single-layer layouts; three-dimensional layout; topological routeing; Integrated circuit layout; Multichip modules; Packaging; Routing; Silicon; Substrates; Transistors; Ultra large scale integration; Very large scale integration; Wire;
Conference_Titel :
Southeastcon '91., IEEE Proceedings of
Conference_Location :
Williamsburg, VA
Print_ISBN :
0-7803-0033-5
DOI :
10.1109/SECON.1991.147719
