DocumentCode

3553706

Title

A process for simultaneous fabrication of vertical NPN and PNP´s Nch, and Pch MOS devices

Author

Beasom, J.D.

Author_Institution

Harris Semiconductor, Melbourne, Florida

Volume

19

fYear

1973

fDate

1973

Firstpage

41

Lastpage

43

Keywords

Fabrication; Frequency; Immune system; Impedance; Linear circuits; Logic functions; MOS devices; Power dissipation; Signal design; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1973 International

Type

conf

DOI

10.1109/IEDM.1973.188643

Filename

1477520