Title :
A process for simultaneous fabrication of vertical NPN and PNP´s Nch, and Pch MOS devices
Author_Institution :
Harris Semiconductor, Melbourne, Florida
Keywords :
Fabrication; Frequency; Immune system; Impedance; Linear circuits; Logic functions; MOS devices; Power dissipation; Signal design; Voltage;
Conference_Titel :
Electron Devices Meeting, 1973 International
DOI :
10.1109/IEDM.1973.188643
