• DocumentCode
    3553717
  • Title

    A double-diffused MNOS transistor as a new non-volatile memory

  • Author

    Endo, Norio ; Nishi, Yoshio

  • Author_Institution
    Toshiba Research and Development Center, Kawasaki, Kanagawa, Japan
  • Volume
    19
  • fYear
    1973
  • fDate
    1973
  • Firstpage
    78
  • Lastpage
    82
  • Abstract
    A new device structure for MNOS non-volatile memory is proposed for the purpose of getting higher writing speed and lower writing voltage. Basic concept is quite analogous to the double-diffused MOS transistor, where the gate oxide is replaced by a combination of the ultrathin oxide of silicon and the silicon nitride. When operated by the hybridization mode of the direct tunneling and the avalanche injection, typical results are as follows: (a) writing time is reduced to less than 100 ns, and (b) writing voltage is about 25 volts which is 10 volts lower than the conventional MNOS structure with the same nitride and oxide thicknesses of 400 Å and 16.5 Å respectively.
  • Keywords
    Breakdown voltage; Logic circuits; MOSFETs; Nonvolatile memory; Pulse measurements; Research and development; Silicon; Threshold voltage; Tunneling; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 1973 International
  • Type

    conf

  • DOI
    10.1109/IEDM.1973.188653
  • Filename
    1477530