A new surface charge analog store

The maximum delay-bandwidth product achievable in a serial charge transfer device is set by charge transfer inefficiency. This limitation can be addressed by improving the transfer efficiency of the transfer elements themselves, or by adopting a parallel architecture so that the number of transfers required for each signal packet is reduced. A new device structure is presented which uses a parallel architecture to solve this problem while maintaining most of the flexibility of the serial transfer approach. In this structure each charge packet is gated into a charge transfer cell where it remains until it is replaced. A non-destructive readout is achieved by sloshing the charge back and forth within the cell to obtain a capacitive pick-up on an overlying output electrode. With a simple experimental device, over 10⁵readings of a single charge packet has been demonstrated. In this experiment the charge was transferred times. The results obtained in this experiment are equivalent to those obtained with a serial charge transfer device with a transfer efficiency of 0.999999.