An investigation of VLSI interconnect failure due to subtractive metal defects

Early failures in VLSI metal interconnects due to subtractive defects are analyzed using a competing risks model. The model considers concurrent failure mechanisms and predicts a bimodal cumulative failure distribution for test structures containing intentional defects. Experimental data for three different metallizations show that, if the defect mechanism dominates as the cause of early failures, the distribution is bimodal. Test structures consist of 1000-μm-long by 3-μm-wide metal stripes. Defect test structures contain semicircular defects located midway along the stripe which remove 50% and 80% of the stripe width, respectively. All tests are performed at 200°C and at a current density in the 10⁶ A/cm² range. Stress voids occurring at grain boundaries are modeled experimentally as test structures with defects located at grain boundaries, and the results show that void/grain-boundary interaction produces a dominant failure mechanism and results in significant early failures