Offset mask charge coupled devices for memory applications

Summary form only given, as follows. This report describes new electrode structures of two-phase and uniphase charge coupled devices using the offset mask technique. Completely sealed electrode structures with polysilicon electrodes and self-aligned gates have been fabricated. Devices of different cell lengths and channel widths were made on 100 p-type substrates. Structures with tungsten and polysilicon electrodes and with implanted barriers and oxide steps for directionality have been compared. Transfer inefficiency has been measured in the range between 10 KHz and 10 MHZ for different channel widths and electrode lengths. Transfer inefficiency of l0^-4 up to 10 MHz clock frequency were observed. The results of detailed measurements and evaluation of the performance of these devices for their use in large high density memories will be presented. In view of these experimental results a comparison with other potential electrode structures will be presented to show that the offset-mask electrode structure presented in this paper is very attractive for charge coupled memories.