Title :
Device scaling: Comparison between bulk and ESFI MOSTs
Author :
Schlotterer, H. ; Tihanyi, J.
Author_Institution :
Siemens AG, Munich, Germany
Abstract :
Summary form only given, as follows. With bulk silicon (Si) MOSTs the decrease of the transistor channel length below a certain limit results in a punch-through current, even at zero gate voltage. To avoid that effect an adequate scaling down of the device has been proposed by Dennard (1972) and others. But as the Si band gap cannot be scaled, the subthreshold characteristics become an important limitation, even if all problems connected with scaling are successfully solved. If ESFI MOSTs are scaled down in the same way, the subthreshold behavior is similar to that of bulk MOSTs. It will be shown in detail that it is possible to realize short channel ESFI MOSTs using a scaling which differs from that proposed by Dennard in a pronounced way. So one possibility - which is not allowed with bulk - is to let all dimensions besides the channel length be unchanged. One can then achieve a higher transconductance without remarkably charging the effective threshold voltage. Even at relatively low impurity concentrations no remarkable punch through effect can be observed. On the other side a higher doping concentration can be used if it is desired to adjust a different threshold voltage. In a similar way we will discuss the transistor behavior if different parameters are scaled down, either separately or with a few parameters together. In conclusion, it is shown that the intrinsic properties of ESFI or SOS generally allow more freedom in the design of scaled transistors. Experimental results are presented with such MOSTs.
Keywords :
Logic design; Logic devices; Photonic band gap; Threshold voltage; Transconductance;
Conference_Titel :
Electron Devices Meeting (IEDM), 1974 International
Conference_Location :
Washington, DC
DOI :
10.1109/IEDM.1974.188808