Title :
A 5000-channel power FET with a new diffused gate structure
Author :
Ozawa, O. ; Sasaki, Y. ; Iwasaki, H. ; Ikoma, H.
Author_Institution :
Toshiba R & D Center, Kawasaki, Japan
Abstract :
This paper describes a new high power, diffused gate, vertical channel, triode-like JFET, fabricated utilizing self-aligned, heavily doped polycrystalline silicon source contacts. These techniques make it possible to realize a high source gate breakdown voltage device. Since the voltage amplification factor of this JFET is determined by the channel space charge region profile, device design requires only gate impurity diffusion depth control, which is very easy. Output I-V characteristics attained for a 4 × 4 mm chip with 5520 channels designed for audio use are; a voltage amplification factor of 5, Idssof 5A at Vds= 10V, a 60V source-gate breakdown voltage and a 200V drain-gate breakdown voltage. The device is operated as a push-pull amplifier which delivers a 50W signal to an 8Ω load.
Keywords :
Breakdown voltage; Crystallization; Etching; FETs; Fabrication; Impurities; Plasma applications; Plasma sources; Plasma temperature; Silicon;
Conference_Titel :
Electron Devices Meeting, 1975 International
DOI :
10.1109/IEDM.1975.188850