A 10 MHz 16K CCD condensed SPS memory requiring only two clocks

A 16,384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 136 × 169 mil²to fit a standard 16-pin package and is organized as four separate shift registers of 4096 bits. A condensed serial-parallel-serial (CSPS) structure was found to provide the highest packing density. Only two external clocks are required driving capacitances of 60pf each at one-half the data transfer rate. Operation at data rates of 100KHz to 10MHz have been demonstrated experimentally, the on-chip power dissipation at 10MHz being less than 20µW/bit.