Limitations on the maximum operating voltage of CMOS integrated circuits

A one-dimensional model has been developed to study the breakdown voltage behavior of an n-channel IGFET in a conventional CMOS integrated circuit. Two parasitic npn bipolar transistors intrinsic to the circuit which shunt the IGFET are found to limit the breakdown voltage below the intrinsic value of the drain/p-tub junction. Turn-on of the parasitics occurs as a result of hole avalanche current flowing in the p-tub at low-level multiplication. Semiquantitative agreement with experimental results is obtained using one adjustable parameter. The model has been used to show how lowering the resistance between the p-tub contact and the n-channel drain reduces the effect of the vertical parasitic. Reduction of the breakdown voltage with reduced channel length has been calculated, as well as the way in which lowered p-tub doping can be used to increase the operating voltage.