C2L: A new high speed, high density bulk CMOS technology

A new structural approach to high speed COS/MOS, C²L, results in significant speed and packing density gains. The CDP 1802, single-chip, 8-bit microprocessor as well as several memory and I/O circuits announced recently by the RCA Solid State Division are fabricated in this new bulk CMOS technology, called C²L or Closed COS/MOS Logic. C²L is a self-aligned silicon gate CMOS technology where the gate completely surrounds the drain. This technique does not require the conventional guardbands of standard Al-gate CMOS and thereby significantly increases packing density as well as device speed, and still retains the inherent advantages of CMOS (very low static power dissipation, high noise immunity and operating voltage from 3 to 15 volts at temperatures ranging from -55°C to 125°C). The basic C²L device structure is presented and compared to standard Al-gate CMOS. The speed advantages of C²L devices are discussed, and data comparing the performance of C²L circuits with comparable standard CMOS devices is presented. Generally, C²L devices show an improvement in packing density by a factor of 3 over standard CMOS and operate at frequencies approximately 4 to 6 times faster than standard CMOS. The fabrication sequence for C²L devices requires 6 photomasks (one less than standard CMOS).