Title :
Minimization of parasitic capacitances in VMOS transistors
Author :
Bhatti, I.S. ; Rodgers, T.J. ; Edwards, J.R.
Author_Institution :
American Microsystems, Inc., Santa Clara, Ca.
Abstract :
Process techniques for the reduction of parasitic capacitances in VMOS transistors (1) have been developed. Significant reductions in gate to drain overlap capacitance and side wall component of the junction capacitance have been achieved for a high performance VMOS process.
Keywords :
Boron; Capacitance-voltage characteristics; Electrodes; Epitaxial layers; MOS devices; Parasitic capacitance; Protection; Silicon; Substrates; Topology;
Conference_Titel :
Electron Devices Meeting, 1976 International
DOI :
10.1109/IEDM.1976.189107
