DocumentCode
3554278
Title
Correlation of fabrication process and electrical device parameter variations
Author
Dutton, R.W. ; Divekar, D.A. ; Gonzalez, A.G. ; Hansen, S.E.
Author_Institution
Stanford University, Stanford California
Volume
22
fYear
1976
fDate
1976
Firstpage
609
Lastpage
613
Abstract
A program for modeling IC fabrication processes is described. Simulated and measured impurity profiles are shown for a bipolar transistor technology. The simulated profiles are used to study sensitivities in electrical device parameters. A comparison of simulated device performance using process models gives parameters which bracket measured results for 35 die across a wafer.
Keywords
Bipolar transistors; Computational modeling; Electrical resistance measurement; Epitaxial growth; Fabrication; Geometry; Impurities; Integrated circuit modeling; Oxidation; Semiconductor process modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1976 International
Type
conf
DOI
10.1109/IEDM.1976.189118
Filename
1478830
Link To Document