DocumentCode
3554401
Title
A high-voltage analog-compatible I2L process
Author
Allstot, D.J. ; Wei, T.S.-T. ; Lui, S.K. ; Gray, P.R. ; Meyer, R.G.
Author_Institution
University of California, Berkeley, California
Volume
23
fYear
1977
fDate
1977
Firstpage
175
Lastpage
177
Abstract
A new I2L process has been developed for application in high-performance analog/digital LSI circuits. High-speed I2L circuitry is realized on the same chip with high-voltage analog bipolar transistors by the addition of a single non-critical masking step, and a phosphorous implant, to a standard 40 volt bipolar process. An experimental test circuit has been designed which shows I2L betas of greater than eight per collector with a minimum average propagation delay of about 40 nS using a 14 micron thick 5 ohm-cm epitaxial layer.
Keywords
Analog computers; Application software; Bipolar transistors; Circuit testing; Doping; Epitaxial layers; Implants; Laboratories; Large scale integration; Propagation delay;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1977 International
Type
conf
DOI
10.1109/IEDM.1977.189197
Filename
1479277
Link To Document