A high-voltage analog-compatible I2L process

A new I²L process has been developed for application in high-performance analog/digital LSI circuits. High-speed I²L circuitry is realized on the same chip with high-voltage analog bipolar transistors by the addition of a single non-critical masking step, and a phosphorous implant, to a standard 40 volt bipolar process. An experimental test circuit has been designed which shows I²L betas of greater than eight per collector with a minimum average propagation delay of about 40 nS using a 14 micron thick 5 ohm-cm epitaxial layer.