The Hi-C RAM cell concept

An MOS dynamic RAM cell concept called the High Capacity (Hi-C) RAM Cell which combines the charge-coupled RAM cell with the one-transistor (1-T) or double-level polysilicon (DLP) structure is described. Analytically, the Hi-C cell is predicted to have a charge storage capcity per unit area 50 - 100% greater than that of the regular 1-T or DLP cells, and a leakage current lower than that of the 1-T and DLP cells. Results of measurements on the first test structures show a 45 - 80% increase in charge capacity and up to 3X reduction in leakage current. In addition, the implant doses required to fabricate the Hi-C cell can be conveniently chosen so that the charge capacity is both maximized and independent of the n-type implant dose in the storage region.