An efficient scaling procedure for Domino CMOS logic

Author

Wurtz, Larry T.

Author_Institution

Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA

fYear

1991

fDate

7-10 Apr 1991

Firstpage

1175

Abstract

The area required by Domino CMOS gates to support a specific response-time performance and capacitive load can be substantially reduced by scaling the NFET chain. A novel scaling procedure is described which requires far less CPU time than previous algorithms. The proposed scaling procedure has resulted in scaled Domino gates with channel area reductions similar to those given by the Monte Carlo/SPICE simulation. This procedure is applicable to other forms of dynamic logic

Keywords

CMOS integrated circuits; integrated logic circuits; logic CAD; logic gates; CMOS gates; Domino CMOS logic; NFET chain scaling; algorithm; capacitive load; channel area reductions; dynamic logic; response-time performance; scaling procedure; CMOS logic circuits; CMOS process; Capacitance; Delay effects; Equations; Inverters; Monte Carlo methods; SPICE; Semiconductor device modeling; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '91., IEEE Proceedings of

Conference_Location

Williamsburg, VA

Print_ISBN

0-7803-0033-5

Type

conf

DOI

10.1109/SECON.1991.147951

Filename

147951

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3554562