Title :
Sub-micron polysilicon Gate CMOS/SOS technology
Author_Institution :
RCA Laboratories, David Sarnoff Research Center, Princeton, NJ
Abstract :
A process sequence incorporating the lateral diffusion of Boron into polycrystalline silicon for the fabrication of CMOS/SOS transistors and integrated circuits is described. The resulting polysilicon gate dimensions and channel lengths are typically between 0.2 µm and 2.0 µm. Yield values associated with these narrow polysilicon lines are shown to be equal to present 5 µm yield values. Ring oscillators have been fabricated having 0.5 µm channel lengths which exhibit propagation delays of 200 ps at 5v. In addition, 10 stage dynamic binary counters have also been fabricated having 0.5 µm channel lengths and a maximum input frequency of 600 MHz at 12v and 200 mW was attained.
Keywords :
Boron; CMOS integrated circuits; CMOS process; CMOS technology; Fabrication; Integrated circuit technology; Integrated circuit yield; Propagation delay; Ring oscillators; Silicon;
Conference_Titel :
Electron Devices Meeting, 1978 International
DOI :
10.1109/IEDM.1978.189348