One-micrometer electron-beam lithography FET technology

An n-channel silicon gate technology, using electron-beam lithography with minimum dimensions of 1 µm, has been implemented for FET logic applications. The six mask process employs semi-recessed oxide isolation and makes extensive use of ion implantation, resist liftoff techniques and reactive ion etching (RIE). A description of the process is given, with particular emphasis or topographical considerations. Implementation of a field etchback after source and drain implant to eliminate a low thick-oxide parasitic device threshold is also discussed.